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LTC3827 Low IQ, Dual, 2-Phase Synchronous Controller
FEATURES

DESCRIPTIO
Wide Output Voltage Range: 0.8V VOUT 10V Low Operating IQ: 80A (One Channel On) Out-of-Phase Controllers Reduce Required Input Capacitance and Power Supply Induced Noise OPTI-LOOP(R) Compensation Minimizes COUT 1% Output Voltage Accuracy Wide VIN Range: 4V to 36V Operation Phase-Lockable Fixed Frequency 140kHz to 650kHz Selectable Continuous, Pulse Skipping or Low Ripple Burst Mode(R) Operation at Light Loads Dual N-Channel MOSFET Synchronous Drive Very Low Dropout Operation: 99% Duty Cycle Adjustable Output Voltage Soft-Start or Tracking Output Current Foldback Limiting Power Good Output Voltage Monitor Output Overvoltage Protection Low Shutdown IQ: 8A Internal LDO Powers Gate Drive from VIN or VOUT Small 5mm x 5mm QFN Package
The LTC(R)3827 is a high performance dual step-down switching regulator controller that drives all N-channel synchronous power MOSFET stages. A constant frequency current mode architecture allows a phase-lockable frequency of up to 650kHz. Power loss and noise due to the ESR of the input capacitor ESR are minimized by operating the two controller output stages out of phase. The 80A no-load quiescent current extends operating life in battery powered systems. OPTI-LOOP compensation allows the transient response to be optimized over a wide range of output capacitance and ESR values. The LTC3827 features a precision 0.8V reference and a power good output indicator. A wide 4V to 36V input supply range encompasses all battery chemistries. Independent TRACK/SS pins for each controller ramp the output voltage during start-up. Current foldback limits MOSFET heat dissipation during short-circuit conditions. The PLLIN/MODE pin selects among Burst Mode operation, pulse skipping mode, or continuous inductor current mode at light loads. For a leaded package version (28-lead SSOP), see the LTC3827-1 datasheet.
, LTC and LT are registered trademarks of Linear Technology Corporation. Burst Mode and OPTI-LOOP are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 5481178, 5929620, 6177787, 6144194, 6100678, 5408150, 6580258, 6304066, 5705919.
APPLICATIO S

Automotive Systems Battery-Operated Digital Devices Distributed DC Power Systems
TYPICAL APPLICATIO
+
4.7F
High Efficiency Dual 8.5V/3.3V Step-Down Converter
VIN 4V TO 36V 1F VIN TG1 3.3H 0.1F BOOST1 SW1 BG1 LTC3827 SENSE1+ 0.015 VOUT1 3.3V 5A SENSE1- VFB1 62.5k 150F 220pF 20k 15k ITH1 SENSE2 - VFB2 ITH2 220pF 15k 20k 192.5k INTVCC TG2 BOOST2 SW2 BG2 PGND SENSE2 + 0.015 VOUT2 8.5V 3.5A 150F 0.1F 7.2H 22F 50V
EFFICIENCY (%)
TRACK/SS1 SGND TRACK/SS2 0.1F 0.1F
3827 TA01
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Efficiency and Power Loss vs Load Current
100 90 80 70 60 50 40 30 20 10 0 0.001 0.01 0.1 0.1 1 10 100 1000 10000 LOAD CURRENT (mA)
3827 TA01b
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100000 EFFICIENCY VIN = 12V; VOUT = 3.3V 10000
POWER LOSS (mW)
1000 100 POWER LOSS 10 1
FIGURE 13 CIRCUIT
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LTC3827
ABSOLUTE
(Note 1)
AXI U
RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW
TRACK/SS1 SENSE1+ PGOOD2 PGOOD1 SW1 VFB1 ITH1 TG1
Input Supply Voltage (VIN).........................36V to - 0.3V Top Side Driver Voltages (BOOST1, BOOST2) ...............................42V to - 0.3V Switch Voltage (SW1, SW2) .........................36V to - 5V (BOOST1-SW1), (BOOST2-SW2) ...............8.5V to - 0.3V RUN1, RUN2 .............................................. 7V to - 0.3V SENSE1+, SENSE2 +, SENSE1-, SENSE2 - Voltages ................................11V to - 0.3V PLLIN/MODE, PLLLPF, Voltages ......... INTVCC to - 0.3V PHASMD, FOLDDIS, TRACK/SS1, TRACK/SS2 Voltages .......................................... INTVCC to - 0.3V EXTVCC ......................................................10V to - 0.3V ITH1, ITH2, VFB1, VFB2 Voltages ..................2.7V to - 0.3V PGOOD1, PGOOD2 Voltages ..................... 8.5V to -0.3V Peak Output Current <10s (TG1, TG2, BG1, BG2) ... 3A INTVCC Peak Output Current ................................ 50mA Operating Temperature Range (Note 2) .. - 40C to 85C Junction Temperature (Note 3) ............................. 125C Storage Temperature Range ................. - 65C to 125C
32 31 30 29 28 27 26 25 SENSE1- 1 PLLLPF 2 PHASMD 3 CLKOUT 4 PLLIN/MODE 5 SGND 6 RUN1 7 RUN2 8 9 10 11 12 13 14 15 16
SENSE2- SENSE2+ FOLDDIS TG2 TRACK/SS2 SW2 VFB2 ITH2
24 BOOST1 23 BG1 22 VIN 33 21 PGND 20 EXTVCC 19 INTVCC 18 BG2 17 BOOST2
UH PACKAGE 32-LEAD (5mm x 5mm) PLASTIC QFN
TJMAX = 125C, JA = 34C/W EXPOSED PAD (PIN 33) IS SGND MUST BE SOLDERED TO PCB
ORDER PART NUMBER LTC3827EUH
UH PART MARKING 3827
Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
SYMBOL VFB1, 2 IVFB1, 2 VREFLNREG VLOADREG PARAMETER Regulated Feedback Voltage Feedback Current Reference Voltage Line Regulation Output Voltage Load Regulation Main Control Loops
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VIN = 12V, VRUN/SS1, 2 = 5V unless otherwise noted.
CONDITIONS (Note 4); ITH1, 2 Voltage = 1.2V (Note 4) VIN = 4V to 30V (Note 4) (Note 4) Measured in Servo Loop; ITH Voltage = 1.2V to 0.7V Measured in Servo Loop; ITH Voltage = 1.2V to 2V ITH1, 2 = 1.2V; Sink/Source 5A (Note 4) (Note 5) RUN1 = 5V, RUN2 = 0V, VFB1 = 0.83V (No Load) RUN1 = OV, RUN2 = 5V, VFB2 = 0.83V (No Load) VRUN1, 2 = 0V RUN1,2 = 5V, VFB1 = VFB2 = 0.83V VIN Ramping Down Measured at VFB1, 2 , Relative to Regulated VFB1, 2 (Each Channel) VSENSE1-, 2 - = VSENSE1+, 2+ = 0V In Dropout 98 99.4

MIN 0.792
TYP 0.800 -5 0.002 0.1 - 0.1 1.55 80 80 8 115 3.5
MAX 0.808 - 50 0.02 0.5 - 0.5
UNITS V nA %/V % % mmho
gm1, 2 IQ
Transconductance Amplifier gm Input DC Supply Current Sleep Mode (Channel 1 On) Sleep Mode (Channel 2 On) Shutdown Sleep Mode (Both Channels) Undervoltage Lockout Feedback Overvoltage Lockout Sense Pins Total Source Current Maximum Duty Factor
125 125 20 160 4 12 - 660
UVLO VOVL ISENSE DFMAX
8
10
2
U
A A A A V % A %
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LTC3827
ELECTRICAL CHARACTERISTICS
SYMBOL ITRACK/SS1, 2 VRUN1, 2 ON VSENSE(MAX) PARAMETER Soft-Start Charge Current RUN Pin ON Threshold Maximum Current Sense Threshold TG Transition Time: Rise Time Fall Time BG Transition Time: Rise Time Fall Time
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VIN = 12V, VRUN/SS1, 2 = 5V unless otherwise noted.
CONDITIONS VTRACK1, 2 = 0V VRUN1, VRUN2 Rising VFB1, 2 = 0.7V,VSENSE1-, 2 - = 3.3V VFB1, 2 = 0.7V,VSENSE1-, 2 - = 3.3V (Note 6) CLOAD = 3300pF CLOAD = 3300pF (Note 6) CLOAD = 3300pF CLOAD = 3300pF
MIN 0.75 0.5 90 80
TYP 1.0 0.7 100 100 50 50 40 40 70 70 180
MAX 1.35 0.9 110 115 90 90 90 80
UNITS A V mV mV ns ns ns ns ns ns ns
TG1, 2 tr TG1, 2 tf BG1, 2 tr BG1, 2 tf TG/BG t1D BG/TG t2D tON(MIN) VINTVCCVIN VLDOVIN VINTVCCEXT VLDOEXT VEXTVCC VLDOHYS fNOM fLOW fHIGH fSYNCMIN fSYNCMAX IPLLLPF
Top Gate Off to Bottom Gate On Delay CLOAD = 3300pF Each Driver Synchronous Switch-On Delay Time Bottom Gate Off to Top Gate On Delay CLOAD = 3300pF Each Driver Top Switch-On Delay Time Minimum On-Time Internal VCC Voltage INTVCC Load Regulation Internal VCC Voltage INTVCC Load Regulation EXTVCC Switchover Voltage EXTVCC Hysteresis Nominal Frequency Lowest Frequency Highest Frequency VPLLLPF = Floating; PLLIN/MODE = DC Voltage VPLLLPF = 0V; PLLIN/MODE = DC Voltage VPLLLPF = INTVCC; PLLIN/MODE = DC Voltage 360 220 475 650 (Note 7) 8.5V < VIN < 30V, VEXTVCC = 0V ICC = 0mA to 20mA, VEXTVCC = 0V VEXTVCC = 8.5V ICC = 0mA to 20mA, VEXTVCC = 8.5V ICC = 20mA, EXTVCC Ramping Positive 4.5 7.2 5.0
INTVCC Linear Regulator 5.25 0.2 7.5 0.2 4.7 0.2 400 250 530 115 800 -5 5 0.1 0.3 1 -12 8 -10 10 -8 12 440 280 580 140 5.5 1.0 7.8 1.0 V % V % V V kHz kHz kHz kHz kHz A A V A % %
Oscillator and Phase-Locked Loop
Minimum Synchronizable Frequency PLLIN/MODE = External Clock; VPLLLPF = 0V Maximum Synchronizable Frequency PLLIN/MODE = External Clock; VPLLLPF = 2V Phase Detector Output Current Sinking Capability Sourcing Capability PGOOD Voltage Low PGOOD Leakage Current PGOOD Trip Level fPLLIN/MODE < fOSC fPLLIN/MODE > fOSC IPGOOD = 2mA VPGOOD = 5V VFB with Respect to Set Regulated Voltage VFB Ramping Negative VFB Ramping Positive
PGOOD Output VPGL IPGOOD VPG
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: The LTC3827E is guaranteed to meet performance specifications from 0C to 70C. Specifications over the -40C to 85C operating temperature range are assured by design, characterization and correlation with statistical process controls. Note 3: TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formulas: TJ = TA + (PD * 34 C/W)
Note 4: The LTC3827 is tested in a feedback loop that servos VITH1, 2 to a specified voltage and measures the resultant VFB1, 2. Note 5: Dynamic supply current is higher due to the gate charge being delivered at the switching frequency. See Applications Information. Note 6: Rise and fall times are measured using 10% and 90% levels. Delay times are measured using 50% levels. Note 7: The minimum on-time condition is specified for an inductor peak-to-peak ripple current 40% of IMAX (see minimum on-time considerations in the Applications Information section).
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LTC3827 TYPICAL PERFOR A CE CHARACTERISTICS
Efficiency and Power Loss vs Output Current
100 90 80 70
EFFICIENCY (%)
Burst Mode OPERATION FORCED CONTINUOUS MODE PULSE SKIPPING MODE
EFFICIENCY (%)
EFFICIENCY (%)
60 50 40 30 VIN = 12V VOUT = 3.3V 20 10 0 0.001 0.01
0.1 0.1 1 10 100 1000 10000 LOAD CURRENT (mA)
3827 G01
FIGURE 13 CIRCUIT
Load Step (Burst Mode Operation)
VOUT 100mV/DIV AC COUPLED
IL 2A/DIV
20s/DIV
FIGURE 13 CIRCUIT VOUT = 3.3V
Inductor Current at Light Load
FORCED CONTINUOUS MODE 2A/DIV BURST MODE PULSE SKIPPING MODE 4s/DIV
3827 G07
FIGURE 13 CIRCUIT VOUT = 3.3V ILOAD = 300A
4
UW
Efficiency vs Load Current
10000
100 90 80 70 60 50 40 0.001 0.01 VIN = 12V VIN = 5V VOUT = 3.3V 98 96 94 92 90 88 86
Efficiency vs Input Voltage
1000
POWER LOSS (mW)
100
10
1
84 82 0.1 1 10 100 1000 10000 LOAD CURRENT (mA)
3827 G02
VOUT = 3.3V 0 5 10 15 20 25 30 INPUT VOLTAGE (V) 35 40
3827 G03
FIGURE 13 CIRCUIT
FFIGURE 13 CIRCUIT
Load Step (Forced Continuous Mode)
Load Step (Pulse Skip Mode)
VOUT 100mV/DIV AC COUPLED
VOUT 100mV/DIV AC COUPLED
IL 2A/DIV
IL 2A/DIV
3827 G04
20s/DIV
3827 G05
20s/DIV
3827 G06
FIGURE 13 CIRCUIT VOUT = 3.3V
FIGURE 13 CIRCUIT VOUT = 3.3V
Soft Start-Up
VOUT2 2V/DIV
Tracking Start-Up
VOUT2 2V/DIV
VOUT1 2V/DIV
VOUT1 2V/DIV
20ms/DIV
FIGURE 13 CIRCUIT
3827 G08
20ms/DIV
FIGURE 13 CIRCUIT
3827 G09
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LTC3827 TYPICAL PERFOR A CE CHARACTERISTICS
Total Input Supply Current vs Input Voltage
350 300
SUPPLY CURRENT (A)
6.0 5.8 5.6 5.4 5.2 5.0 4.8 4.6 4.4 4.2 4.0 -45 -25 35 15 -5 55 TEMPERATURE (C) 75 95 EXTVCC FALLING EXTVCC RISING INTVCC
EXTVCC AND INTVCC VOLTAGES (V)
INTVCC VOLTAGE (V)
250 300A LOAD 200 150 100 50 0 5 10 25 20 15 INPUT VOLTAGE (V) 30 35
3827 G10
NO LOAD
Maximum Current Sense Voltage vs ITH Voltage
100
CURRENT SENSE THRESHOLD (mV)
80 60 40 20 0 -20
CURRENT SENSE THRESHOLD (mV)
PULSE SKIPPING FORCED CONTINUOUS BURST MODE (RISING) BURST MODE (FALLING)
INPUT CURRENT (A)
10% Duty Cycle -40 0 0.2 1.0 0.4 0.6 0.8 ITH PIN VOLTAGE (V) 1.2 1.4
-700 0 123456789 VSENSE COMMON MODE VOLTAGE (V) 10
0 0 10 20 30 40 50 60 70 80 90 100 DUTY CYCLE (%)
3827 G15
Foldback Current Limit
120
MAXIMUM CURRENT SENSE VOLTAGE (V)
TRACK/SS = 1V
100
QUIESCENT CURRENT (A)
80 60 40 20 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 FEEDBACK VOLTAGE (V)
3827 G16
INPUT CURRENT (A)
UW
3827 G13
EXTVCC Switchover and INTVCC Voltages vs Temperature
5.50 5.45 5.40 5.35 5.30 5.25 5.20 5.15 5.10 5.05 5.00
INTVCC Line Regulation
0
5
10
15 20 25 30 INPUT VOLTAGE (V)
35
40
3827 G12
3827 G11
Sense Pins Total Input Bias Current
200 100 0 -100 -200 -300 -400 -500 -600
120 100 80 60 40 20
Maximum Current Sense Threshold vs Duty Cycle
3827 G14
Quiescent Current vs Temperature
100 95 90 85 80 75 70 65 60 -45 -30 -15 0 15 30 45 60 TEMPERATURE (C) 75 90
SENSE Pins Total Input Bias Current vs ITH
12 VSENSE = 3.3V
PLLIN/MODE = 0V
10 8 6 4 2 0
0
0.2
0.4
0.6 0.8 1.0 ITH VOLTAGE (V)
1.2
1.4
3827 G17
3827 G18
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LTC3827 TYPICAL PERFOR A CE CHARACTERISTICS
TRACK/SS Pull-Up Current vs Temperature
1.20 1.15
TRACK/SS CURRENT (A)
0.95 0.90
REGULATED FEEDBACK VOLTAGE (mV)
RUN PIN VOLTAGE (V)
1.10 1.05 1.00 0.95 0.90 0.85 0.80 -45 -30 -15 0 15 30 45 60 TEMPERATURE (C) 75 90
Sense Pins Total Input Current vs Temperature
200 100 0
INPUT CURRENT (A)
VOUT = 10V VOUT = 3.3V 700 20 600
INPUT CURRENT (A)
FREQUENCY (kHz)
-100 -200 -300 -400 -500 -600 -700 -800 -45 -30 -15 VOUT = OV
0 15 30 45 60 TEMPERATURE (C)
Undervoltage Lockout Threshold vs Temperature
4.2 4.1 404 402
FREQUENCY (kHz)
3.9 3.8 3.7 3.6 3.5 3.4 3.3 3.2 -45 -30 -15 FALLING RISING
400 398 396 394 392
SHUTDOWN CURRENT (A)
4.0
INTVCC VOLTAGE (V)
0 15 30 45 60 TEMPERATURE (C)
6
UW
75
Shutdown (RUN) Threshold vs Temperature
1.00
Regulated Feedback Voltage vs Temperature
808 806 804 802 800 798 796 794 792 -45 -30 -15 0 15 30 45 60 TEMPERATURE (C) 75 90
0.85 0.80 0.75 0.70 0.65 0.60 0.55 0.50 -45 -30 -15 0 15 30 45 60 TEMPERATURE (C) 75 90
3827 G19
3827 G20
3827 G21
Shutdown Current vs Input Voltage
25 800
Oscillator Frequency vs Temperature
VPLLLPF = INTVCC VPLLLPF = FLOAT VPLLLPF = GND
15
500 400 300 200
10
5 100 0 90 5 10 25 20 15 INPUT VOLTAGE (V) 30 35
3827 G23
0 -45 -25
35 15 -5 55 TEMPERATURE (C)
75
95
3827 G22
3827 G24
Oscillator Frequency vs Input Voltage
12 10 8 6 4 2
Shutdown Current vs Temperature
75
90
5
10
25 20 15 INPUT VOLTAGE (V)
30
35
3827 G26
0 -45 -30 -15
0 15 30 45 60 TEMPERATURE (C)
75
90
3827 G25
3827 G27
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LTC3827
PI FU CTIO S
SENSE1-, SENSE2- (Pins 1, 9): The (-) Input to the Differential Current Comparators. PLLLPF (Pin 2): The phase-locked loop's lowpass filter is tied to this pin when synchronizing to an external clock. Alternatively, tie this pin to GND, INTVCC or leave floating to select 250kHz, 530kHz or 400kHz switching frequency. PHASMD (Pin 3): Control Input to Phase Selector which determines the phase relationships between controller 1, controller 2 and the CLKOUT signal. CLKOUT (Pin 4): Output Clock Signal available to daisychain other controller ICs for additional MOSFET driver stages/phases. PLLIN/MODE (Pin 5): External Synchronization Input to Phase Detector and Forced Continuous Control Input. When an external clock is applied to this pin, the phase-locked loop will force the rising TG1 signal to be synchronized with the rising edge of the external clock. In this case, an R-C filter must be connected to the PLLLPF pin. When not synchronizing to an external clock, this input, which acts on both controllers, determines how the LTC3827 operates at light loads. Pulling this pin below 0.7V selects Burst Mode operation. Tying this pin to INTVCC forces continuous inductor current operation. Tying this pin to a voltage greater than 0.9V and less than INTVCC -0.5V selects pulse skipping operation. SGND (Pins 6, 33): Small Signal Ground common to both controllers, must be routed separately from high current grounds to the common (-) terminals of the CIN capacitors. The Exposed Pad is SGND. It must be soldered to PCB ground for rated thermal performance. RUN1, RUN2 (Pins 7, 8): Digital Run Control Inputs for Each Controller. Forcing either of these pins below 0.7V shuts down that controller. Forcing both of these pins below 0.7V shuts down the entire LTC3827, reducing quiescent current to approximately 8A. FOLDDIS (Pin 14): Foldback Current Disable Input Pin. Driving this pin high (to INTVCC) disables foldback current limiting during short-circuit or overcurrent conditions. INTVCC (Pin 19): Output of the Internal Linear Low Dropout Regulator. The driver and control circuits are powered from this voltage source. Must be decoupled to power ground with a minimum of 4.7F tantalum or other low ESR capacitor. EXTVCC (Pin 20): External Power Input to an Internal LDO Connected to INTVCC. This LDO supplies INTVCC power, bypassing the internal LDO powered from VIN whenever EXTVCC is higher than 4.7V. See EXTVCC Connection in the Applications Information section. Do not exceed 10V on this pin. PGND (Pin 21): Driver Power Ground. Connects to the sources of bottom (synchronous) N-channel MOSFETs, anodes of the Schottky rectifiers and the (-) terminal(s) of CIN. VIN (Pin 22): Main Supply Pin. A bypass capacitor should be tied between this pin and the signal ground pin. BG1, BG2 (Pins 23, 18): High Current Gate Drives for Bottom (Synchronous) N-Channel MOSFETs. Voltage swing at these pins is from ground to INTVCC. BOOST1, BOOST2 (Pins 24, 17): Bootstrapped Supplies to the Top Side Floating Drivers. Capacitors are connected between the BOOST and SW pins and Schottky diodes are tied between the BOOST and INTVCC pins. Voltage swing at the BOOST pins is from INTVCC to (VIN + INTVCC). SW1, SW2 (Pins 25, 16): Switch Node Connections to Inductors. Voltage swing at these pins is from a Schottky diode (external) voltage drop below ground to VIN. TG1, TG2 (Pins 26, 15): High Current Gate Drives for Top N-Channel MOSFETs. These are the outputs of floating drivers with a voltage swing equal to INTVCC - 0.5V superimposed on the switch node voltage SW. PGOOD1 (Pin 27): Open-Drain Logic Output. PGOOD1 is pulled to ground when the voltage on the VFB1 pin is not within 10% of its set point. PGOOD2 (Pin 28): Open-Drain Logic Output. PGOOD2 is pulled to ground when the voltage on VFB2 pin is not within 10% of its set point. TRACK/SS1, TRACK/SS2 (Pins 29, 13): External Tracking and Soft-Start Input. The LTC3827 regulates the VFB1,2 voltage to the smaller of 0.8V or the voltage on the TRACK/ SS1,2 pin. A internal 1A pull-up current source is connected to this pin. A capacitor to ground at this pin sets the ramp time to final regulated output voltage. Alternatively,
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LTC3827
PI FU CTIO S
a resistor divider on another voltage supply connected to this pin allows the LTC3827 output to track the other supply during startup. I TH1, I TH2 (Pins 30, 12): Error Amplifier Outputs and Switching Regulator Compensation Points. Each associated channel's current comparator trip point increases with this control voltage. VFB1, VFB2 (Pins 31, 11): Receives the remotely sensed feedback voltage for each controller from an external resistive divider across the output. SENSE1+, SENSE2+ (Pins 32, 10): The (+) Input to the Differential Current Comparators. The ITH pin voltage and controlled offsets between the SENSE - and SENSE+ pins in conjunction with RSENSE set the current trip threshold. Exposed Pad (Pin 33): SGND. Must be soldered to the PCB.
FU CTIO AL DIAGRA
PLLIN/MODE FIN 5 100k PHASMD 3 PLLLPF 2 RLP CLP CLKOUT 4 PGOOD1 27 OSCILLATOR PHASE DET
CLK1 CLK2 - + VFB1 - + - 0.72V 0.88V VFB2 - + INTVCC-0.5V - + PLLIN/MODE 0.8V - + BURSTEN FC 0.45V 2(VFB) SLOPE COMP 0.72V ICMP + - 0.88V R Q S Q
PGOOD2 28
+ IR SENSE + 32, 10 SENSE - 1, 9 VFB 31, 11
VIN VIN 22 4.7V EXTVCC 20 INTVCC + - 5V/ 7.5V LDO 0.5A
SHDN RST 2(VFB)
+
19 SGND 6, 33 INTERNAL SUPPLY RUN 7, 8
8
W
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INTVCC DUPLICATE FOR SECOND CONTROLLER CHANNEL BOOST 24, 17 TG 26, 15 SW 25, 16 SWITCH LOGIC BOT BURSTEN 0.4V + - B SLEEP SHDN INTVCC BG 23, 18 PGND 21 L DB
VIN
DROP OUT DET
TOP BOT TOP ON FC
CB D CIN
COUT VOUT
RSENSE
-
++
6mV
-
- +
- EA + OV + -
VFB TRACK/SS 0.80V
RB
RA
0.88V
ITH 30,12
CC
6V
FOLDBACK
CC2 1A TRACK/SS 29, 13 CSS
RC
SHDN 14 FOLDDIS
3827 FD
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LTC3827
OPERATIO
Main Control Loop The LTC3827 uses a constant frequency, current mode step-down architecture with the two controller channels operating 180 degrees out of phase. During normal operation, each external top MOSFET is turned on when the clock for that channel sets the RS latch, and is turned off when the main current comparator, ICMP, resets the RS latch. The peak inductor current at which ICMP trips and resets the latch is controlled by the voltage on the ITH pin, which is the output of the error amplifier EA. The error amplifier compares the output voltage feedback signal at the VFB pin, (which is generated with an external resistor divider connected across the output voltage, VOUT, to ground) to the internal 0.800V reference voltage. When the load current increases, it causes a slight decrease in VFB relative to the reference, which causes the EA to increase the ITH voltage until the average inductor current matches the new load current. After the top MOSFET is turned off each cycle, the bottom MOSFET is turned on until either the inductor current starts to reverse, as indicated by the current comparator IR, or the beginning of the next clock cycle. INTVCC/EXTVCC Power Power for the top and bottom MOSFET drivers and most other internal circuitry is derived from the INTVCC pin. When the EXTVCC pin is left open or tied to a voltage less than 4.7V, an internal 5V low dropout linear regulator supplies INTVCC power from VIN. If EXTVCC is taken above 4.7V, the 5V regulator is turned off and a 7.5V low dropout linear regulator is enabled that supplies INTVCC power from EXTVCC. If EXTVCC is less than 7.5V (but greater than 4.7V), the 7.5V regulator is in dropout and INTVCC is approximately equal to EXTVCC. When EXTVCC is greater than 7.5V (up to an absolute maximum rating of 10V), INTVCC is regulated to 7.5V. Using the EXTVCC pin allows the INTVCC power to be derived from a high efficiency external source such as one of the LTC3827 switching regulator outputs. Each top MOSFET driver is biased from the floating bootstrap capacitor CB, which normally recharges during each off cycle through an external diode when the top MOSFET turns off. If the input voltage VIN decreases to a voltage
U
(Refer to Functional Diagram)
close to VOUT, the loop may enter dropout and attempt to turn on the top MOSFET continuously. The dropout detector detects this and forces the top MOSFET off for about one twelfth of the clock period every tenth cycle to allow CB to recharge. Shutdown and Start-Up (RUN1, RUN2 and TRACK/ SS1, TRACK/SS2 Pins) The two channels of the LTC3827 can be independently shut down using the RUN1 and RUN2 pins. Pulling either of these pins below 0.7V shuts down the main control loop for that controller. Pulling both pins low disables both controllers and most internal circuits, including the INTVCC regulator, and the LTC3827 draws only 8A of quiescent current. Releasing either RUN pin allows an internal 0.5A current to pull up the pin and enable that controller. Alternatively, the RUN pin may be externally pulled up or driven directly by logic. Be careful not to exceed the Absolute Maximum rating of 6V on this pin. The start-up of each controller's output voltage VOUT is controlled by the voltage on the TRACK/SS1 and TRACK/ SS2 pin. When the voltage on the TRACK/SS pin is less than the 0.8V internal reference, the LTC3827 regulates the VFB voltage to the TRACK/SS pin voltage instead of the 0.8V reference. This allows the TRACK/SS pin to be used to program a soft start by connecting an external capacitor from the TRACK/SS pin to SGND. An internal 1A pull-up current charges this capacitor creating a voltage ramp on the TRACK/SS pin. As the TRACK/SS voltage rises linearly from 0V to 0.8V (and beyond), the output voltage VOUT rises smoothly from zero to its final value. Alternatively the TRACK/SS pin can be used to cause the start-up of VOUT to "track" that of another supply. Typically, this requires connecting to the TRACK/SS pin an external resistor divider from the other supply to ground (see Applications Information section). When the corresponding RUN pin is pulled low to disable a controller, or when VIN drops below its undervoltage lockout threshold of 3.7V, the TRACK/SS pin is pulled low by an internal MOSFET. When in undervoltage lockout, both controllers are disabled and the external MOSFETs are held off.
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LTC3827
OPERATIO
Light Load Current Operation (Burst Mode Operation, Pulse Skipping, or Continuous Conduction) (PLLIN/MODE Pin) The LTC3827 can be enabled to enter high efficiency Burst Mode operation, constant frequency pulse skipping mode, or forced continuous conduction mode at low load currents. To select Burst Mode operation, tie the PLLIN/ MODE pin to a DC voltage below 0.8V (e.g., SGND). To select forced continuous operation, tie the PLLIN/MODE pin to INTVCC. To select pulse-skipping mode, tie the PLLIN/MODE pin to a DC voltage greater than 0.8V and less than INTVCC - 0.5V. When a controller is enabled for Burst Mode operation, the peak current in the inductor is set to approximately onetenth of the maximum sense voltage even though the voltage on the ITH pin indicates a lower value. If the average inductor current is lower than the load current, the error amplifier EA will decrease the voltage on the ITH pin. When the ITH voltage drops below 0.4V, the internal sleep signal goes high (enabling "sleep" mode) and both external MOSFETs are turned off. The ITH pin is then disconnected from the output of the EA and "parked" at 0.425V. In sleep mode, much of the internal circuitry is turned off, reducing the quiescent current that the LTC3827 draws. If one channel is shut down and the other channel is in sleep mode, the LTC3827 draws only 80A of quiescent current. If both channels are in sleep mode, the LTC3827 draws only 115A of quiescent current. In sleep mode, the load current is supplied by the output capacitor. As the output voltage decreases, the EA's output begins to rise. When the output voltage drops enough, the ITH pin is reconnected to the output of the EA, the sleep signal goes low, and the controller resumes normal operation by turning on the top external MOSFET on the next cycle of the internal oscillator. When a controller is enabled for Burst Mode operation, the inductor current is not allowed to reverse. The reverse current comparator (IR) turns off the bottom external MOSFET just before the inductor current reaches zero, preventing it from reversing and going negative. Thus, the controller operates in discontinuous operation. In forced continuous operation, the inductor current is allowed to reverse at light loads or under large transient
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(Refer to Functional Diagram)
conditions. The peak inductor current is determined by the voltage on the ITH pin, just as in normal operation. In this mode, the efficiency at light loads is lower than in Burst Mode operation. However, continuous has the advantages of lower output ripple and less interference to audio circuitry. In forced continuous mode, the output ripple is independent of load current. When the PLLIN/MODE pin is connected for pulse-skipping mode or clocked by an external clock source to use the phase-locked loop (see Frequency Selection and PhaseLocked Loop section), the LTC3827 operates in PWM pulse skipping mode at light loads. In this mode, constant frequency operation is maintained down to approximately 1% of designed maximum output current. At very light loads, the current comparator ICMP may remain tripped for several cycles and force the external top MOSFET to stay off for the same number of cycles (i.e., skipping pulses). The inductor current is not allowed to reverse (discontinuous operation). This mode, like forced continuous operation, exhibits low output ripple as well as low audio noise and reduced RF interference as compared to Burst Mode operation. It provides higher low current efficiency than forced continuous mode, but not nearly as high as Burst Mode operation. Frequency Selection and Phase-Locked Loop (PLLLPF and PLLIN/MODE Pins) The selection of switching frequency is a tradeoff between efficiency and component size. Low frequency operation increases efficiency by reducing MOSFET switching losses, but requires larger inductance and/or capacitance to maintain low output ripple voltage. The switching frequency of the LTC3827's controllers can be selected using the PLLLPF pin. If the PLLIN/MODE pin is not being driven by an external clock source, the PLLLPF pin can be floated, tied to INTVCC, or tied to SGND to select 400kHz, 530kHz, or 250kHz, respectively. A phase-locked loop (PLL) is available on the LTC3827 to synchronize the internal oscillator to an external clock source that is connected to the PLLIN/MODE pin. In this case, a series R-C should be connected between the PLLLPF pin and SGND to serve as the PLL's loop filter. The
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LTC3827
OPERATIO
LTC3827 phase detector adjusts the voltage on the PLLLPF pin to align the turn-on of controller 1's external top MOSFET to the rising edge of the synchronizing signal. Thus, the turn-on of controller 2's external top MOSFET is 180 degrees out of phase to the rising edge of the external clock source. The typical capture range of the LTC3827's phaselocked loop is from approximately 115kHz to 800kHz, with a guarantee over all manufacturing variations to be between 140kHz and 650kHz. In other words, the LTC3827's PLL is guaranteed to lock to an external clock source whose frequency is between 140kHz and 650kHz. The typical input clock thresholds on the PLLIN/MODE pin are 1.6V (rising) and 1.2V (falling). PolyPhase Applications (CLKOUT and PHASMD Pins) The LTC3827 features two pins (CLKOUT and PHASMD) that allow other controller ICs to be daisy-chained with the LTC3827 in PolyPhase(R) applications. The clock output signal on the CLKOUT pin can be used to synchronize additional power stages in a multiphase power supply solution feeding a single, high current output or multiple separate outputs. The PHASMD pin is used to adjust the phase of the CLKOUT signal as well as the relative phases between the two internal controllers, as summarized in Table 1. The phases are calculated relative to the zero degrees phase being defined as the rising edge of the top gate driver output of controller 1 (TG1).
Table 1
VPHASMD GND Floating INTVCC CONTROLLER 2 PHASE 180 180 240 CLKOUT PHASE 60 90 120
Output Overvoltage Protection An overvoltage comparator guards against transient overshoots as well as other more serious conditions that may overvoltage the output. When the VFB pin rises by more than 10% above its regulation point of 0.800V, the top MOSFET is turned off and the bottom MOSFET is turned on until the overvoltage condition is cleared.
PolyPhase is a registered trademark of Linear Technology Corporation.
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(Refer to Functional Diagram)
Power Good (PGOOD1 and PGOOD2) Pins Each PGOOD pin is connected to an open drain of an internal N-channel MOSFET. The MOSFET turns on and pulls the PGOOD pin low when the corresponding VFB pin voltage is not within 10% of the 0.8V reference voltage. The PGOOD pin is also pulled low when the corresponding RUN pin is low (shut down) or when the LTC3827 is in undervoltage lockout. When the VFB pin voltage is within the 10% requirement, the MOSFET is turned off and the pin is allowed to be pulled up by an external resistor to a source of up to 8.5V. Foldback Current (FOLDDIS Pin) When the output voltage falls to less than 70% of its nominal level, foldback current limiting is activated, progressively lowering the peak current limit in proportion to the severity of the overcurrent or short-circuit condition. Foldback current limiting is disabled during the soft-start interval (as long as the VFB voltage is keeping up with the TRACK/SS voltage) or when the FOLDDIS pin is pulled high to INTVCC. THEORY AND BENEFITS OF 2-PHASE OPERATION Why the need for 2-phase operation? Up until the 2-phase family, constant-frequency dual switching regulators operated both channels in phase (i.e., single-phase operation). This means that both switches turned on at the same time, causing current pulses of up to twice the amplitude of those for one regulator to be drawn from the input capacitor and battery. These large amplitude current pulses increased the total RMS current flowing from the input capacitor, requiring the use of more expensive input capacitors and increasing both EMI and losses in the input capacitor and battery. With 2-phase operation, the two channels of the dualswitching regulator are operated 180 degrees out of phase. This effectively interleaves the current pulses drawn by the switches, greatly reducing the overlap time where they add together. The result is a significant reduction in total RMS input current, which in turn allows less expensive input capacitors to be used, reduces shielding requirements for EMI and improves real world operating efficiency.
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LTC3827
OPERATIO U
(Refer to Functional Diagram)
5V SWITCH 20V/DIV 3.3V SWITCH 20V/DIV INPUT CURRENT 5A/DIV INPUT VOLTAGE 500mV/DIV
IIN(MEAS) = 2.53ARMS
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IIN(MEAS) = 1.55ARMS
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(a)
(b)
Figure 1. Input Waveforms Comparing Single-Phase (a) and 2-Phase (b) Operation for Dual Switching Regulators Converting 12V to 5V and 3.3V at 3A Each. The Reduced Input Ripple with the 2-Phase Regulator Allows Less Expensive Input Capacitors, Reduces Shielding Requirements for EMI and Improves Efficiency
Figure 1 compares the input waveforms for a representative single-phase dual switching regulator to the LTC3827 2-phase dual switching regulator. An actual measurement of the RMS input current under these conditions shows that 2-phase operation dropped the input current from 2.53ARMS to 1.55ARMS. While this is an impressive reduction in itself, remember that the power losses are proportional to IRMS2, meaning that the actual power wasted is reduced by a factor of 2.66. The reduced input ripple voltage also means less power is lost in the input power path, which could include batteries, switches, trace/connector resistances and protection circuitry. Improvements in both conducted and radiated EMI also directly accrue as a result of the reduced RMS input current and voltage. Of course, the improvement afforded by 2-phase operation is a function of the dual switching regulator's relative
3.0 2.5
INPUT RMS CURRENT (A)
duty cycles which, in turn, are dependent upon the input voltage VIN (Duty Cycle = VOUT/VIN). Figure 2 shows how the RMS input current varies for single-phase and 2-phase operation for 3.3V and 5V regulators over a wide input voltage range. It can readily be seen that the advantages of 2-phase operation are not just limited to a narrow operating range, for most applications is that 2-phase operation will reduce the input capacitor requirement to that for just one channel operating at maximum current and 50% duty cycle. The schematic on the first page is a basic LTC3827 application circuit. External component selection is driven by the load requirement, and begins with the selection of RSENSE and the inductor value. Next, the power MOSFETs are selected. Finally, CIN and COUT are selected.
SINGLE PHASE DUAL CONTROLLER
2.0 1.5 1.0 0.5 0 2-PHASE DUAL CONTROLLER
VO1 = 5V/3A VO2 = 3.3V/3A 0 10 20 30 INPUT VOLTAGE (V) 40
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Figure 2. RMS Input Current Comparison
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LTC3827
APPLICATIO S I FOR ATIO
RSENSE Selection for Output Current
RSENSE is chosen based on the required output current. The current comparator has a maximum threshold of 100mV/RSENSE and an input common mode range of SGND to 10V. The current comparator threshold sets the peak of the inductor current, yielding a maximum average output current IMAX equal to the peak value less half the peak-to-peak ripple current, IL. Allowing a margin for variations in the IC and external component values yields:
RSENSE =
80mV IMAX
When using the controller in very low dropout conditions, the maximum output current level will be reduced due to the internal compensation required to meet stability criterion for buck regulators operating at greater than 50% duty factor. A curve is provided in the Typical Performance Characteristics section to estimate this reduction in peak output current level depending upon the operating duty factor. Operating Frequency and Synchronization The choice of operating frequency, is a trade-off between efficiency and component size. Low frequency operation improves efficiency by reducing MOSFET switching losses, both gate charge loss and transition loss. However, lower frequency operation requires more inductance for a given amount of ripple current. The internal oscillator for each of the LTC3827's controllers runs at a nominal 400kHz frequency when the PLLLPF pin is left floating and the PLLIN/MODE pin is a DC low or high. Pulling the PLLLPF to INTVCC selects 530kHz operation; pulling the PLLLPF to SGND selects 250kHz operation. Alternatively, the LTC3827 will phase-lock to a clock signal applied to the PLLIN/MODE pin with a frequency between 140kHz and 650kHz (see Phase-Locked Loop and Frequency Synchronization). Inductor Value Calculation The operating frequency and inductor selection are interrelated in that higher operating frequencies allow the use
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of smaller inductor and capacitor values. So why would anyone ever choose to operate at lower frequencies with larger components? The answer is efficiency. A higher frequency generally results in lower efficiency because of MOSFET gate charge losses. In addition to this basic trade-off, the effect of inductor value on ripple current and low current operation must also be considered. The inductor value has a direct effect on ripple current. The inductor ripple current IL decreases with higher inductance or frequency and increases with higher VIN:
IL = V 1 VOUT 1 - OUT ( f)(L) VIN
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Accepting larger values of IL allows the use of low inductances, but results in higher output voltage ripple and greater core losses. A reasonable starting point for setting ripple current is IL=0.3(IMAX). The maximum IL occurs at the maximum input voltage. The inductor value also has secondary effects. The transition to Burst Mode operation begins when the average inductor current required results in a peak current below 10% of the current limit determined by RSENSE. Lower inductor values (higher IL) will cause this to occur at lower load currents, which can cause a dip in efficiency in the upper range of low current operation. In Burst Mode operation, lower inductance values will cause the burst frequency to decrease. Inductor Core Selection Once the value for L is known, the type of inductor must be selected. High efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite or molypermalloy cores. Actual core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance selected. As inductance increases, core losses go down. Unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. Ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite
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LTC3827
APPLICATIO S I FOR ATIO
core material saturates "hard," which means that inductance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate! Power MOSFET and Schottky Diode (Optional) Selection Two external power MOSFETs must be selected for each controller in the LTC3827: one N-channel MOSFET for the top (main) switch, and one N-channel MOSFET for the bottom (synchronous) switch. The peak-to-peak drive levels are set by the INTVCC voltage. This voltage is typically 5V during start-up (see EXTVCC Pin Connection). Consequently, logic-level threshold MOSFETs must be used in most applications. The only exception is if low input voltage is expected (VIN < 5V); then, sub-logic level threshold MOSFETs (VGS(TH) < 3V) should be used. Pay close attention to the BVDSS specification for the MOSFETs as well; most of the logic level MOSFETs are limited to 30V or less. Selection criteria for the power MOSFETs include the "ON" resistance RDS(ON), Miller capacitance CMILLER, input voltage and maximum output current. Miller capacitance, CMILLER, can be approximated from the gate charge curve usually provided on the MOSFET manufacturers' data sheet. CMILLER is equal to the increase in gate charge along the horizontal axis while the curve is approximately flat divided by the specified change in VDS. This result is then multiplied by the ratio of the application applied VDS to the Gate charge curve specified VDS. When the IC is operating in continuous mode the duty cycles for the top and bottom MOSFETs are given by:
Main Switch Duty Cycle = VOUT VIN VIN - VOUT VIN
Synchronous Switch Duty Cycle =
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The MOSFET power dissipations at maximum output current are given by:
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PMAIN =
()
2 VOUT IMAX 1 + RDS(ON) + VIN 2 I VIN MAX RDR C MILLER * 2 1 1 + ( f VINTVCC - VTHMIN VTHMIN
( )( ) ( )(
)
)
2 VIN - VOUT IMAX 1 + RDS(ON) VIN where is the temperature dependency of RDS(ON) and RDR (approximately 2) is the effective driver resistance at the MOSFET's Miller threshold voltage. VTHMIN is the typical MOSFET minimum threshold voltage.
PSYNC =
( )( )
Both MOSFETs have I2R losses while the topside N-channel equation includes an additional term for transition losses, which are highest at high input voltages. For VIN < 20V the high current efficiency generally improves with larger MOSFETs, while for VIN > 20V the transition losses rapidly increase to the point that the use of a higher RDS(ON) device with lower CMILLER actually provides higher efficiency. The synchronous MOSFET losses are greatest at high input voltage when the top switch duty factor is low or during a short-circuit when the synchronous switch is on close to 100% of the period. The term (1+) is generally given for a MOSFET in the form of a normalized RDS(ON) vs Temperature curve, but = 0.005/C can be used as an approximation for low voltage MOSFETs. The optional Schottky diodes D3 and D4 shown in Figure 14 conduct during the dead-time between the conduction of the two power MOSFETs. This prevents the body diode of the bottom MOSFET from turning on, storing charge during the dead-time and requiring a reverse recovery period that could cost as much as 3% in efficiency at high VIN. A 1A to 3A Schottky is generally a good compromise for both regions of operation due to the relatively small average current. Larger diodes result in additional transition losses due to their larger junction capacitance.
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APPLICATIO S I FOR ATIO
CIN and COUT Selection The selection of CIN is simplified by the 2-phase architecture and its impact on the worst-case RMS current drawn through the input network (battery/fuse/capacitor). It can be shown that the worst-case capacitor RMS current occurs when only one controller is operating. The controller with the highest (VOUT)(IOUT) product needs to be used in the formula below to determine the maximum RMS capacitor current requirement. Increasing the output current drawn from the other controller will actually decrease the input RMS ripple current from its maximum value. The out-of-phase technique typically reduces the input capacitor's RMS ripple current by a factor of 30% to 70% when compared to a single phase power supply solution. In continuous mode, the source current of the top MOSFET is a square wave of duty cycle (VOUT)/(VIN). To prevent large voltage transients, a low ESR capacitor sized for the maximum RMS current of one channel must be used. The maximum RMS capacitor current is given by: CIN Required IRMS IMAX VOUT VIN - VOUT VIN
[( )(
This formula has a maximum at VIN = 2VOUT, where IRMS = IOUT/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that capacitor manufacturers' ripple current ratings are often based on only 2000 hours of life. This makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. Several capacitors may be paralleled to meet size or height requirements in the design. Due to the high operating frequency of the LTC3827, ceramic capacitors can also be used for CIN. Always consult the manufacturer if there is any question.
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The benefit of the LTC3827 2-phase operation can be calculated by using the equation above for the higher power controller and then calculating the loss that would have resulted if both controller channels switched on at the same time. The total RMS power lost is lower when both controllers are operating due to the reduced overlap of current pulses required through the input capacitor's ESR. This is why the input capacitor's requirement calculated above for the worst-case controller is adequate for the dual controller design. Also, the input protection fuse resistance, battery resistance, and PC board trace resistance losses are also reduced due to the reduced peak currents in a 2-phase system. The overall benefit of a multiphase design will only be fully realized when the source impedance of the power supply/battery is included in the efficiency testing. The sources of the top MOSFETs should be placed within 1cm of each other and share a common CIN(s). Separating the sources and CIN may produce undesirable voltage and current resonances at VIN. A small (0.1F to 1F) bypass capacitor between the chip VIN pin and ground, placed close to the LTC3827, is also suggested. A 10 resistor placed between CIN (C1) and the VIN pin provides further isolation between the two channels. The selection of COUT is driven by the effective series resistance (ESR). Typically, once the ESR requirement is satisfied, the capacitance is adequate for filtering. The output ripple (VOUT) is approximated by:
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)]
1/ 2
1 VOUT IRIPPLE ESR + 8 fCOUT
where f is the operating frequency, COUT is the output capacitance and IRIPPLE is the ripple current in the inductor. The output ripple is highest at maximum input voltage since IRIPPLE increases with input voltage.
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Setting Output Voltage
INPUT CURRENT (A)
The LTC3827 output voltages are each set by an external feedback resistor divider carefully placed across the output, as shown in Figure 3. The regulated output voltage is determined by:
R VOUT = 0 . 8 V * 1 + B RA
To improve the frequency response, a feed-forward capacitor, CFF, may be used. Great care should be taken to route the VFB line away from noise sources, such as the inductor or the SW line. SENSE+ and SENSE- Pins The common mode input range of the current comparator is from 0V to 10V. Continuous linear operation is provided throughout this range allowing output voltages from 0.8V to 10V. The input stage of the current comparator requires that current either be sourced or sunk from the SENSE pins depending on the output voltage, as shown in the curve in Figure 4. If the output voltage is below 1.5V, current will flow out of both SENSE pins to the main output. In these cases, the output can be easily pre-loaded by the VOUT resistor divider to compensate for the current comparator's negative input bias current. Since VFB is servoed to the 0.8V reference voltage, RA in Figure 3 should be chosen to be less than 0.8V/ISENSE, with ISENSE determined from Figure 4 at the specified output voltage.
VOUT RB CFF
1/2 LTC3827 VFB
RA
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Figure 3. Setting Output Voltage
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200 100 0 -100 -200 -300 -400 -500 -600 -700 0 123456789 VSENSE COMMON MODE VOLTAGE (V) 10
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Figure 4. SENSE Pins Input Bias Current vs Common Mode (Output) Voltage
1/2 LTC3827 TRACK/SS CSS SGND
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Figure 5. Using the TRACK/SS Pin to Program Soft-Start
Tracking and Soft-Start (TRACK/SS Pins) The start-up of each VOUT is controlled by the voltage on the respective TRACK/SS pin. When the voltage on the TRACK/SS pin is less than the internal 0.8V reference, the LTC3827 regulates the VFB pin voltage to the voltage on the TRACK/SS pin instead of 0.8V. The TRACK/SS pin can be used to program an external soft-start function or to allow VOUT to "track" another supply during start-up. Soft-start is enabled by simply connecting a capacitor from the TRACK/SS pin to ground, as shown in Figure 5. An internal 1A current source charges up the capacitor, providing a linear ramping voltage at the TRACK/SS pin. The LTC3827 will regulate the VFB pin (and hence VOUT) according to the voltage on the TRACK/SS pin, allowing VOUT to rise smoothly from 0V to its final regulated value. The total soft-start time will be approximately:
t SS = C SS *
0 . 8V 1 A
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Alternatively, the TRACK/SS pin can be used to track two (or more) supplies during start-up, as shown qualitatively in Figures 6a and 6b. To do this, a resistor divider should be connected from the master supply (VX) to the TRACK/ SS pin of the slave supply (VOUT), as shown in Figure 7. During start-up VOUT will track VX according to the ratio set by the resistor divider:
+ R TRACKB VOUT RA R = * TRACKA VX R TRACKA R A + RB
For coincident tracking (VOUT = VX during start-up), RA = RTRACKA RB = RTRACKB
VX (MASTER)
OUTPUT VOLTAGE
VOUT (SLAVE)
TIME
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(6a) Coincident Tracking
VX (MASTER)
OUTPUT VOLTAGE
VOUT (SLAVE)
TIME
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(6b) Ratiometric Tracking
Figure 6. Two Different Modes of Output Voltage Tracking
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Vx VOUT RB RA RTRACKB TRACK/SS RTRACKA
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1/2 LTC3827 VFB
Figure 7. Using the TRACK/SS Pin for Tracking
INTVCC Regulators The LTC3827 features two separate internal P-channel low dropout linear regulators (LDO) that supply power at the INTVCC pin from either the VIN supply pin or the EXTVCC pin, respectively, depending on the connection of the EXTVCC pin. INTVCC powers the gate drivers and much of the LTC3827's internal circuitry. The VIN LDO regulates the voltage at the INTVCC pin to 5V and the EXTVCC LDO regulates it to 7.5V. Each of these can supply a peak current of 50mA and must be bypassed to ground with a minimum of 4.7F tantalum, 10F special polymer, or low ESR electrolytic capacitor. A ceramic capacitor with a minimum value of 4.7F can also be used if a 1 resistor is added in series with the capacitor. No matter what type of bulk capacitor is used, an additional 1F ceramic capacitor placed directly adjacent to the INTVCC and PGND IC pins is highly recommended. Good bypassing is needed to supply the high transient currents required by the MOSFET gate drivers and to prevent interaction between the channels. High input voltage applications in which large MOSFETs are being driven at high frequencies may cause the maximum junction temperature rating for the LTC3827 to be exceeded. The INTVCC current, which is dominated by the gate charge current, may be supplied by either the 5V VIN LDO or the 7.5V EXTVCC LDO. When the voltage on the EXTVCC pin is less than 4.7V, the VIN LDO is enabled. Power dissipation for the IC in this case is highest and is equal to VIN * INTVCC. The gate charge current is dependent on operating frequency as discussed in the Efficiency Considerations section. The junction temperature can be estimated by using the equations given in Note 2 of the Electrical Characteristics. For example, the LTC3827 INTVCC
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current is limited to less than 24mA from a 24V supply when in the G package and not using the EXTVCC supply: TJ = 70C + (24mA)(24V)(95C/W) = 125C To prevent the maximum junction temperature from being exceeded, the input supply current must be checked while operating in continuous conduction mode (PLLIN/MODE = INTVCC) at maximum VIN. When the voltage applied to EXTVCC rises above 4.7V, the VIN LDO is turned off and the EXTVCC LDO is enabled. The EXTVCC LDO remains on as long as the voltage applied to EXTVCC remains above 4.5V. The EXTVCC LDO attempts to regulate the INTVCC voltage to 7.5V, so while EXTVCC is less than 7.5V, the LDO is in dropout and the INTVCC voltage is approximately equal to EXTVCC. When EXTVCC is greater than 7.5V up to an absolute maximum of 10V, INTVCC is regulated to 7.5V. Using the EXTVCC LDO allows the MOSFET driver and control power to be derived from one of the LTC3827's switching regulator outputs (4.7V VOUT 10V) during normal operation and from the VIN LDO when the output is out of regulation (e.g., startup, short-circuit). If more current is required through the EXTVCC LDO than is specified, an external Schottky diode can be added between the EXTVCC and INTVCC pins. Do not apply more than 10V to the EXTVCC pin and make sure than EXTVCC VIN. Significant efficiency and thermal gains can be realized by powering INTVCC from the output, since the VIN current resulting from the driver and control currents will be scaled by a factor of (Duty Cycle)/(Switcher Efficiency). For 5V to 10V regulator outputs, this means connecting the EXTVCC pin directly to VOUT. Tying the EXTVCC pin to a 5V supply reduces the junction temperature in the previous example from 125C to: TJ = 70C + (24mA)(5V)(95C/W) = 81C However, for 3.3V and other low voltage outputs, additional circuitry is required to derive INTVCC power from the output. The following list summarizes the four possible connections for EXTVCC: 1. EXTVCC Left Open (or Grounded). This will cause INTVCC to be powered from the internal 5V regulator
LTC3827 TG1 CIN VIN
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VIN 1F
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+
BAT85 0.22F BAT85
VN2222LL N-CH RSENSE
BAT85 VOUT
EXTVCC
SW
L1
+
BG1 N-CH PGND
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COUT
Figure 8. Capacitive Charge Pump for EXTVCC
resulting in an efficiency penalty of up to 10% at high input voltages. 2. EXTVCC Connected directly to VOUT. This is the normal connection for a 5V to 10V regulator and provides the highest efficiency. 3. EXTVCC Connected to an External supply. If an external supply is available in the 5V to 10V range, it may be used to power EXTVCC providing it is compatible with the MOSFET gate drive requirements. 4. EXTVCC Connected to an Output-Derived Boost Network. For 3.3V and other low voltage regulators, efficiency gains can still be realized by connecting EXTVCC to an output-derived voltage that has been boosted to greater than 4.7V. This can be done with the capacitive charge pump shown in Figure 8. Topside MOSFET Driver Supply (CB, DB) External bootstrap capacitors CB connected to the BOOST pins supply the gate drive voltages for the topside MOSFETs. Capacitor CB in the Functional Diagram is charged though external diode DB from INTVCC when the SW pin is low. When one of the topside MOSFETs is to be turned on, the driver places the CB voltage across the gatesource of the desired MOSFET. This enhances the MOSFET and turns on the topside switch. The switch node voltage, SW, rises to VIN and the BOOST pin follows. With the topside MOSFET on, the boost voltage is above
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the input supply: VBOOST = VIN + VINTVCC. The value of the boost capacitor CB needs to be 100 times that of the total input capacitance of the topside MOSFET(s). The reverse breakdown of the external Schottky diode must be greater than VIN(MAX). When adjusting the gate drive level, the final arbiter is the total input current for the regulator. If a change is made and the input current decreases, then the efficiency has improved. If there is no change in input current, then there is no change in efficiency. Fault Conditions: Current Limit and Current Foldback The LTC3827 includes current foldback to help limit load current when the output is shorted to ground. If the output falls below 70% of its nominal output level, then the maximum sense voltage is progressively lowered from 100mV to 30mV. Under short-circuit conditions with very low duty cycles, the LTC3827 will begin cycle skipping in order to limit the short-circuit current. In this situation the bottom MOSFET will be dissipating most of the power but less than in normal operation. The short-circuit ripple current is determined by the minimum on-time tON(MIN) of the LTC3827 (180ns), the input voltage and inductor value: IL(SC) = tON(MIN) (VIN/L) The resulting short-circuit current is:
ISC = 10mV 1 - IL(SC) R SENSE 2
Fault Conditions: Overvoltage Protection (Crowbar) The overvoltage crowbar is designed to blow a system input fuse when the output voltage of the regulator rises much higher than nominal levels. The crowbar causes huge currents to flow, that blow the fuse to protect against a shorted top MOSFET if the short occurs while the controller is operating. A comparator monitors the output for overvoltage conditions. The comparator (OV) detects overvoltage faults greater than 10% above the nominal output voltage. When this condition is sensed, the top MOSFET is turned off and the bottom MOSFET is turned on until the overvoltage condition is cleared. The bottom MOSFET remains on continuously for as long as the OV condition persists; if VOUT returns to a safe level, normal operation automati900 800 700
FREQUENCY (kHz)
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cally resumes. A shorted top MOSFET will result in a high current condition which will open the system fuse. The switching regulator will regulate properly with a leaky top MOSFET by altering the duty cycle to accommodate the leakage. Phase-Locked Loop and Frequency Synchronization The LTC3827 has a phase-locked loop (PLL) comprised of an internal voltage-controlled oscillator (VCO) and a phase detector. This allows the turn-on of the top MOSFET of controller 1 to be locked to the rising edge of an external clock signal applied to the PLLIN/MODE pin. The turn-on of controller 2's top MOSFET is thus 180 degrees out of phase with the external clock. The phase detector is an edge sensitive digital type that provides zero degrees phase shift between the external and internal oscillators. This type of phase detector does not exhibit false lock to harmonics of the external clock. The output of the phase detector is a pair of complementary current sources that charge or discharge the external filter network connected to the PLLLPF pin. The relationship between the voltage on the PLLLPF pin and operating frequency, when there is a clock signal applied to PLLIN/ MODE, is shown in Figure 9 and specified in the Electrical Characteristics table. Note that the LTC3827 can only be synchronized to an external clock whose frequency is within range of the LTC3827's internal VCO, which is nominally 115kHz to 800kHz. This is guaranteed to be
600 500 400 300 200 100 0 0 0.5 1 1.5 2 PLLLPF PIN VOLTAGE (V) 2.5
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Figure 9. Relationship Between Oscillator Frequency and Voltage at the PLLLPF Pin When Synchronizing to an External Clock
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APPLICATIO S I FOR ATIO
between 140kHz and 650kHz. A simplified block diagram is shown in Figure 10. If the external clock frequency is greater than the internal oscillator's frequency, fOSC, then current is sourced continuously from the phase detector output, pulling up the PLLLPF pin. When the external clock frequency is less than fOSC, current is sunk continuously, pulling down the PLLLPF pin. If the external and internal frequencies are the same but exhibit a phase difference, the current sources turn on for an amount of time corresponding to the phase difference. The voltage on the PLLLPF pin is adjusted until the phase and frequency of the internal and external oscillators are identical. At the stable operating point, the phase detector output is high impedance and the filter capacitor CLP holds the voltage. The loop filter components, CLP and RLP, smooth out the current pulses from the phase detector and provide a stable input to the voltage-controlled oscillator. The filter components CLP and RLP determine how fast the loop acquires lock. Typically RLP = 10k and CLP is 2200pF to 0.01F. Typically, the external clock (on PLLIN/MODE pin) input high threshold is 1.6V, while the input low threshold is 1.2V.
2.4V RLP CLP PLLIN/ MODE EXTERNAL OSCILLATOR PLLLPF DIGITAL PHASE/ FREQUENCY DETECTOR
OSCILLATOR
Figure 10. Phase-Locked Loop Block Diagram
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Table 2 summarizes the different states in which the PLLLPF pin can be used.
Table 2
PLLLPF PIN 0V Floating VIN RC Loop Filter PLLIN/MODE PIN DC Voltage DC Voltage DC Voltage Clock Signal FREQUENCY 250kHz 400kHz 530kHz Phase-Locked to External Clock
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Minimum On-Time Considerations Minimum on-time tON(MIN) is the smallest time duration that the LTC3827 is capable of turning on the top MOSFET. It is determined by internal timing delays and the gate charge required to turn on the top MOSFET. Low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that
t ON(MIN) < VOUT VIN( f)
If the duty cycle falls below what can be accommodated by the minimum on-time, the controller will begin to skip cycles. The output voltage will continue to be regulated, but the ripple voltage and current will increase. The minimum on-time for the LTC3827 is approximately 180ns. However, as the peak sense voltage decreases the minimum on-time gradually increases up to about 200ns. This is of particular concern in forced continuous applications with low ripple current at light loads. If the duty cycle drops below the minimum on-time limit in this situation, a significant amount of cycle skipping can occur with correspondingly larger current and voltage ripple.
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LTC3827
APPLICATIO S I FOR ATIO
Efficiency Considerations
The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Percent efficiency can be expressed as: %Efficiency = 100% - (L1 + L2 + L3 + ...) where L1, L2, etc. are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in LTC3827 circuits: 1) IC VIN current, 2) INTVCC regulator current, 3) I2R losses, 4) Topside MOSFET transition losses. 1. The VIN current has two components: the first is the DC supply current given in the Electrical Characteristics table, which excludes MOSFET driver and control currents; the second is the current drawn from the 3.3V linear regulator output. VIN current typically results in a small (<0.1%) loss. 2. INTVCC current is the sum of the MOSFET driver and control currents. The MOSFET driver current results from switching the gate capacitance of the power MOSFETs. Each time a MOSFET gate is sw----itched from low to high to low again, a packet of charge dQ moves from INTVCC to ground. The resulting dQ/dt is a current out of INTVCC that is typically much larger than the control circuit current. In continuous mode, IGATECHG =f(QT+QB), where QT and QB are the gate charges of the topside and bottom side MOSFETs. Supplying INTVCC power through the EXTVCC switch input from an output-derived source will scale the VIN current required for the driver and control circuits by a factor of (Duty Cycle)/(Efficiency). For example, in a 20V to 5V application, 10mA of INTVCC current results in approximately 2.5mA of VIN current. This reduces the mid-current loss from 10% or more (if the driver was powered directly from VIN) to only a few percent. 3. I2R losses are predicted from the DC resistances of the fuse (if used), MOSFET, inductor, current sense resistor, and input and output capacitor ESR. In continuous
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mode the average output current flows through L and RSENSE, but is "chopped" between the topside MOSFET and the synchronous MOSFET. If the two MOSFETs have approximately the same RDS(ON), then the resistance of one MOSFET can simply be summed with the resistances of L, RSENSE and ESR to obtain I2R losses. For example, if each RDS(ON) = 30m, RL = 50m, RSENSE = 10m and RESR = 40m (sum of both input and output capacitance losses), then the total resistance is 130m. This results in losses ranging from 3% to 13% as the output current increases from 1A to 5A for a 5V output, or a 4% to 20% loss for a 3.3V output. Efficiency varies as the inverse square of VOUT for the same external components and output power level. The combined effects of increasingly lower output voltages and higher currents required by high performance digital systems is not doubling but quadrupling the importance of loss terms in the switching regulator system! 4. Transition losses apply only to the topside MOSFET(s), and become significant only when operating at high input voltages (typically 15V or greater). Transition losses can be estimated from: Transition Loss = (1.7) VIN2 IO(MAX) CRSS f Other "hidden" losses such as copper trace and internal battery resistances can account for an additional 5% to 10% efficiency degradation in portable systems. It is very important to include these "system" level losses during the design phase. The internal battery and fuse resistance losses can be minimized by making sure that CIN has adequate charge storage and very low ESR at the switching frequency. A 25W supply will typically require a minimum of 20F to 40F of capacitance having a maximum of 20m to 50m of ESR. The LTC3728L 2-phase architecture typically halves this input capacitance requirement over competing solutions. Other losses including Schottky conduction losses during dead-time and inductor core losses generally account for less than 2% total additional loss.
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LTC3827
APPLICATIO S I FOR ATIO
Checking Transient Response The regulator loop response can be checked by looking at the load current transient response. Switching regulators take several cycles to respond to a step in DC (resistive) load current. When a load step occurs, VOUT shifts by an amount equal to ILOAD (ESR), where ESR is the effective series resistance of COUT. ILOAD also begins to charge or discharge COUT generating the feedback error signal that forces the regulator to adapt to the current change and return VOUT to its steady-state value. During this recovery time VOUT can be monitored for excessive overshoot or ringing, which would indicate a stability problem. OPTI-LOOP compensation allows the transient response to be optimized over a wide range of output capacitance and ESR values. The availability of the ITH pin not only allows optimization of control loop behavior but also provides a DC coupled and AC filtered closed loop response test point. The DC step, rise time and settling at this test point truly reflects the closed loop response. Assuming a predominantly second order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. The bandwidth can also be estimated by examining the rise time at the pin. The ITH external components shown in Figure 13 circuit will provide an adequate starting point for most applications. The ITH series RC-CC filter sets the dominant pole-zero loop compensation. The values can be modified slightly (from 0.5 to 2 times their suggested values) to optimize transient response once the final PC layout is done and the particular output capacitor type and value have been determined. The output capacitors need to be selected because the various types and values determine the loop
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gain and phase. An output current pulse of 20% to 80% of full-load current having a rise time of 1s to 10s will produce output voltage and ITH pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. Placing a power MOSFET directly across the output capacitor and driving the gate with an appropriate signal generator is a practical way to produce a realistic load step condition. The initial output voltage step resulting from the step change in output current may not be within the bandwidth of the feedback loop, so this signal cannot be used to determine phase margin. This is why it is better to look at the ITH pin signal which is in the feedback loop and is the filtered and compensated control loop response. The gain of the loop will be increased by increasing RC and the bandwidth of the loop will be increased by decreasing CC. If RC is increased by the same factor that CC is decreased, the zero frequency will be kept the same, thereby keeping the phase shift the same in the most critical frequency range of the feedback loop. The output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. A second, more severe transient is caused by switching in loads with large (>1F) supply bypass capacitors. The discharged bypass capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator can alter its delivery of current quickly enough to prevent this sudden step change in output voltage if the load switch resistance is low and it is driven quickly. If the ratio of CLOAD to COUT is greater than 1:50, the switch rise time should be controlled so that the load rise time is limited to approximately 25 * CLOAD. Thus a 10F capacitor would require a 250s rise time, limiting the charging current to about 200mA.
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LTC3827
APPLICATIO S I FOR ATIO
Design Example As a design example for one channel, assume VIN = 12V(nominal), VIN = 22V(max), VOUT = 1.8V, IMAX = 5A, and f = 250kHz. The inductance value is chosen first based on a 30% ripple current assumption. The highest value of ripple current occurs at the maximum input voltage. Tie the PLLLPF pin to GND, generating 250kHz operation. The minimum inductance for 30% ripple current is:
IL =
VOUT VOUT 1- ( f)(L) VIN
A 4.7H inductor will produce 23% ripple current and a 3.3H will result in 33%. The peak inductor current will be the maximum DC value plus one half the ripple current, or 5.84A, for the 3.3H value. Increasing the ripple current will also help ensure that the minimum on-time of 180ns is not violated. The minimum on-time occurs at maximum VIN: t ON(MIN) = VOUT VIN(MAX )f = 1 . 8V = 327n s 22V(250kHz)
The RSENSE resistor value can be calculated by using the maximum current sense voltage specification with some accommodation for tolerances:
R SENSE
80mV 0 . 012 5 . 84A
Choosing 1% resistors: R1 = 25.5k and R2 = 32.4k yields an output voltage of 1.816V. The power dissipation on the top side MOSFET can be easily estimated. Choosing a Fairchild FDS6982S dual
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MOSFET results in: RDS(ON) = 0.035/0.022, CMILLER = 215pF. At maximum input voltage with T(estimated) = 50C:
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PMAIN =
1 . 8V 2 (5) [1+ (0 . 005)(50 C - 25 C)] * 22V 5A (0 . 0 3 5) + (22V )2 ( 4)(215pF ) * 2 1 1 5 - 2 . 3 + 2 . 3 ( 300kHz ) = 332mW
A short-circuit to ground will result in a folded back current of:
ISC = 25mV 1 120ns(22V) - = 2 . 1A 0 . 01 2 3 . 3 H
with a typical value of RDS(ON) and = (0.005/C)(20) = 0.1. The resulting power dissipated in the bottom MOSFET is:
PSYNC =
22V - 1 . 8 V (2 . 1A )2 (1 . 125) (0 . 022) 22V = 100mW
which is less than under full-load conditions. CIN is chosen for an RMS current rating of at least 3A at temperature assuming only this channel is on. COUT is chosen with an ESR of 0.02 for low output ripple. The output ripple in continuous mode will be highest at the maximum input voltage. The output voltage ripple due to ESR is approximately: VORIPPLE = RESR (IL) = 0.02(1.67A) = 33mVP-P
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LTC3827
APPLICATIO S I FOR ATIO
PC Board Layout Checklist When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the IC. These items are also illustrated graphically in the layout diagram of Figure 11. Figure 12 illustrates the current waveforms present in the various branches of the 2-phase synchronous regulators operating in the continuous mode. Check the following in your layout: 1. Are the top N-channel MOSFETs M1 and M3 located within 1cm of each other with a common drain connection at CIN? Do not attempt to split the input decoupling for the two channels as it can cause a large resonant loop.
TRACK/SS1 ITH1 VFB1 SENSE1 + SENSE1 - PLLLPF PHASMD CLKOUT fIN PLLIN/MODE RUN1 RUN2 SGND SENSE2
-
PGOOD2 PGOOD1 TG1 SW1
BOOST1 BG1 VIN CVIN PGND EXTVCC INTVCC BG2 BOOST2 CB2 SW2 TG2 FOLDIS
+
+
SENSE2 + VFB2 ITH2 TRACK/SS2
Figure 11. Recommended Printed Circuit Layout Diagram
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2. Are the signal and power grounds kept separate? The combined IC signal ground pin and the ground return of CINTVCC must return to the combined COUT (-) terminals. The path formed by the top N-channel MOSFET, Schottky diode and the CIN capacitor should have short leads and PC trace lengths. The output capacitor (-) terminals should be connected as close as possible to the (-) terminals of the input capacitor by placing the capacitors next to each other and away from the Schottky loop described above. 3. Do the LTC3827 VFB pins' resistive dividers connect to the (+) terminals of COUT? The resistive divider must be connected between the (+) terminal of COUT and signal
RPU2 PGOOD2 VPULL-UP (<8.5V) RPU1 PGOOD1 L1 RSENSE VOUT1 VPULL-UP (<8.5V) CB1 M1 M2 D1 RIN 1F CERAMIC COUT1
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+
GND
CINTVCC
VIN 1F CERAMIC M3
CIN
COUT2
+
M4
D2
RSENSE VOUT2 L2
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LTC3827
APPLICATIO S I FOR ATIO
ground. The feedback resistor connections should not be along the high current input feeds from the input capacitor(s). 4. Are the SENSE - and SENSE + leads routed together with minimum PC trace spacing? The filter capacitor between SENSE + and SENSE - should be as close as possible to the IC. Ensure accurate current sensing with Kelvin connections at the SENSE resistor. 5. Is the INTVCC decoupling capacitor connected close to the IC, between the INTVCC and the power ground pins? This capacitor carries the MOSFET drivers current peaks. An additional 1F ceramic capacitor placed immediately next to the INTVCC and PGND pins can help improve noise performance substantially.
SW1
VIN RIN CIN
SW2
BOLD LINES INDICATE HIGH SWITCHING CURRENT. KEEP LINES TO A MINIMUM LENGTH.
Figure 12. Branch Current Waveforms
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6. Keep the switching nodes (SW1, SW2), top gate nodes (TG1, TG2), and boost nodes (BOOST1, BOOST2) away from sensitive small-signal nodes, especially from the opposites channel's voltage and current sensing feedback pins. All of these nodes have very large and fast moving signals and therefore should be kept on the "output side" of the LTC3827 and occupy minimum PC trace area. 7. Use a modified "star ground" technique: a low impedance, large copper area central grounding point on the same side of the PC board as the input and output capacitors with tie-ins for the bottom of the INTVCC decoupling capacitor, the bottom of the voltage feedback resistive divider and the SGND pin of the IC.
L1 RSENSE1 VOUT1 D1 COUT1 RL1 L2 RSENSE2 VOUT2 D2 COUT2 RL2
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APPLICATIO S I FOR ATIO
PC Board Layout Debugging Start with one controller on at a time. It is helpful to use a DC-50MHz current probe to monitor the current in the inductor while testing the circuit. Monitor the output switching node (SW pin) to synchronize the oscilloscope to the internal oscillator and probe the actual output voltage as well. Check for proper performance over the operating voltage and current range expected in the application. The frequency of operation should be maintained over the input voltage range down to dropout and until the output load drops below the low current operation threshold--typically 10% of the maximum designed current level in Burst Mode operation. The duty cycle percentage should be maintained from cycle to cycle in a well-designed, low noise PCB implementation. Variation in the duty cycle at a subharmonic rate can suggest noise pickup at the current or voltage sensing inputs or inadequate loop compensation. Overcompensation of the loop can be used to tame a poor PC layout if regulator bandwidth optimization is not required. Only after each controller is checked for its individual performance should both controllers be turned on at the same time. A particularly difficult region of operation is when one controller channel is nearing its current comparator trip point when the other channel is turning on its top MOSFET. This occurs around 50% duty cycle on either channel due to the phasing of the internal clocks and may cause minor duty cycle jitter. Reduce VIN from its nominal level to verify operation of the regulator in dropout. Check the operation of the under-
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voltage lockout circuit by further lowering VIN while monitoring the outputs to verify operation. Investigate whether any problems exist only at higher output currents or only at higher input voltages. If problems coincide with high input voltages and low output currents, look for capacitive coupling between the BOOST, SW, TG, and possibly BG connections and the sensitive voltage and current pins. The capacitor placed across the current sensing pins needs to be placed immediately adjacent to the pins of the IC. This capacitor helps to minimize the effects of differential noise injection due to high frequency capacitive coupling. If problems are encountered with high current output loading at lower input voltages, look for inductive coupling between CIN, Schottky and the top MOSFET components to the sensitive current and voltage sensing traces. In addition, investigate common ground path voltage pickup between these components and the SGND pin of the IC. An embarrassing problem, which can be missed in an otherwise properly working switching regulator, results when the current sensing leads are hooked up backwards. The output voltage under this improper hookup will still be maintained but the advantages of current mode control will not be realized. Compensation of the voltage loop will be much more sensitive to component selection. This behavior can be investigated by temporarily shorting out the current sensing resistor--don't worry, the regulator will still maintain control of the output voltage.
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LTC3827
TYPICAL APPLICATIO
CSS1 0.01F CITH1A 150pF CITH1 1200pF 39pF
RITH1 9.53k RA1 68.1k
RB1 215k ITH1 VFB1
C1 1nF
C2 1nF RA2 22.1k CITH2 560pF RITH2 35.7k RB2 215k
SENSE2 - SENSE2 + VFB2 ITH2 TRACK/SS2
INTVCC BG2 BOOST2 SW2 TG2 FOLDDIS D2 CB2 0.47F
CITH2A 100pF CSS2 0.01F
39pF MTOP1, MTOP2, MBOT1, MBOT2: Si7848DP L1: CDEP105-3R2M L2: CDEP105-7R2M COUT1, COUT2 = SANYO 10TPD150M
3827 TA02
Efficiency vs Load Current
100 90 80 70
VOUT = 3.3V VOUT = 8.5V
Start-Up
VOUT2 2V/DIV SW1 5V/DIV VOUT1 2V/DIV SW2 5V/DIV
EFFICIENCY (%)
60
50
40
30
20
10
20ms/DIV
0.1 1 10 100 1000 10000 LOAD CURRENT (mA) 3827 F13
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0 0.001 0.01
Figure 13. High Efficiency Dual 8.5V/3.3V Step-Down Converter
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LTC3827 TRACK/SS1 PGOOD2 PGOOD1 TG1 SW1 CB1 0.47F PLLLPF PHASMD CLKOUT PLLIN/MODE SGND RUN1 RUN2 EXTVCC CINT2 1F CINT1 4.7F VIN PGND CIN1 10F CIN2 10F BOOST1 BG1 D1 VIN 12V MBOT1 MTOP1 L1 3.3H RSNS1 12m COUT1 150F VOUT1 3.3V 5A 100k 100k SENSE1 + SENSE1 - MTOP2 L2 7.2H RSNS2 12m MBOT2 VOUT2 8.5V COUT2 3.5A 150F
SW Node Waveform
1s/DIV
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LTC3827
TYPICAL APPLICATIO
CSS1 0.01F CITH1A 100pF CITH1 470pF RB1 365k
RITH1 10k RA1 69.8k
C1 1nF
C2 1nF RA2 39.2k CITH2 330P CITH2A 100P CSS2 0.01F RITH2 15k RB2 432k
SENSE2 - SENSE2 + VFB2 ITH2 TRACK/SS2
INTVCC BG2 BOOST2 SW2 TG2 FOLDDIS D2 CB2 0.47F
MTOP1, MTOP2, MBOT1, MBOT2: Si7848DP L1: CDEP105-3R2M L2: CDEP105-7R2M COUT1, COUT2 = SANYO 10TPD150M
Efficiency vs Load Current
100 90 80 70 VOUT = 5V VOUT = 9.5V
Start-Up
VOUT2 2V/DIV VOUT1 2V/DIV
EFFICIENCY (%)
60 50 40 30 20 10 0 0.001 0.01 0.1 1 10 100 1000 10000 LOAD CURRENT (mA) 3827 F16
20ms/DIV
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High Efficiency Dual 5V/9.5V Step-Down Converter
LTC3827 ITH1 VFB1 SENSE1 + SENSE1 - PLLLPF PHASMD CLKOUT PLLIN/MODE SGND RUN1 RUN2 EXTVCC CINT2 1F CINT1 4.7F VIN PGND CIN1 10F CIN2 10F TRACK/SS1 PGOOD2 PGOOD1 TG1 SW1 CB1 0.47F BOOST1 BG1 D1 VIN 12V MBOT1 MTOP1 L1 3.3H RSNS1 12m COUT1 150F VOUT1 5V 5A 100k 100k MTOP2 L2 7.2H RSNS2 12m COUT2 150F MBOT2 VOUT2 9.5V 3A
3827 TA03
SW Node Waveform
SW1 5V/DIV SW2 5V/DIV
1s/DIV
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LTC3827
TYPICAL APPLICATIO
CSS1 0.01F CITH1A 100pF CITH1 330pF RB1 385k ITH1 VFB1 SENSE1 + C1 1nF SENSE1 - PLLLPF PHASMD CLKOUT PLLIN/MODE SGND RUN1 RUN2 C2 1nF RA2 39.2k CITH2 330pF CITH2A 100pF CSS2 0.01F 22pF RITH2 15k RB2 353k SENSE2 - SENSE2 + VFB2 ITH2 TRACK/SS2 EXTVCC INTVCC BG2 BOOST2 SW2 TG2 FOLDDIS MBOT2 D4 MTOP2 D2 CB2 0.47F CINT2 1F CINT1 4.7F VIN PGND CIN1 10F CIN2 10F
High Efficiency Synchronizable Dual 5V/8V Step-Down Converter
RITH1 15k RA1 40k
10k
10nF
MTOP1, MTOP2, MBOT1, MBOT2: Si7848DP L1: CDEP105-3R2M L2: CDEP105-7R2M COUT1, COUT2 = SANYO 10TPD150M
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LTC3827 TRACK/SS1 PGOOD2 PGOOD1 TG1 SW1 CB1 0.47F BOOST1 MBOT1 BG1 D1 VIN 12V D3 MTOP1 L1 3.3H RSNS1 20m COUT1 150F VOUT1 5V 5A 100k 100k L2 7.2H RSNS2 20m VOUT2 8V COUT2 2A 150F
3827 TA04
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LTC3827
TYPICAL APPLICATIO
CSS1 0.01F CITH1A 210pF CITH1 2.2nF
47pF RB1 385k ITH1 VFB1 SENSE1 + C1 1nF SENSE1 - PLLLPF PHASMD CLKOUT PLLIN/MODE SGND RUN1 RUN2 C2 1nF SENSE2 - SENSE2 + VFB2 EXTVCC INTVCC BG2 BOOST2 SW2 TG2 FOLDDIS MBOT2 MTOP2 D2 CB2 0.47F CINT2 1F CINT1 4.7F VIN PGND CIN1 10F CIN2 10F
RITH1 7k RA1 402k
RA2 316k CITH2 2.2nF CITH2A 100pF CSS2 0.01F RITH2 10k RB2 125k
ITH2 TRACK/SS2
MTOP1, MTOP2, MBOT1, MBOT2: Si7848DP L1: CDEP105-2R2M L2: CDEP105-2R2M COUT1, COUT2 = SANYO 10TPD150M
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High Efficiency Dual 1.2V/1V Step-Down Converter
LTC3827 TRACK/SS1 PGOOD2 PGOOD1 TG1 SW1 CB1 0.47F BOOST1 BG1 D1 VIN 12V MBOT1 MTOP1 L1 2.2H RSNS1 15m COUT1 150F VOUT1 1.0V 5A 100k 100k L2 2.2H RSNS2 15m VOUT2 1.2V COUT2 5A 150F
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LTC3827
PACKAGE DESCRIPTIO U
UH Package 32-Lead Plastic QFN (5mm x 5mm)
(Reference LTC DWG # 05-08-1693)
0.70 0.05 PACKAGE OUTLINE 0.25 0.05 0.50 BSC RECOMMENDED SOLDER PAD LAYOUT 5.00 0.10 (4 SIDES) PIN 1 TOP MARK (NOTE 6) 0.75 0.05 0.00 - 0.05 BOTTOM VIEW--EXPOSED PAD R = 0.115 TYP 31 32 0.40 0.10 1 2 PIN 1 NOTCH R = 0.30 TYP OR 0.35 x 45 CHAMFER 3.45 0.10 (4-SIDES)
(UH32) QFN 1004
5.50 0.05 4.10 0.05 3.45 0.05 (4 SIDES)
0.200 REF NOTE: 1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE M0-220 VARIATION WHHD-(X) (TO BE APPROVED) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
0.25 0.05 0.50 BSC
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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LTC3827
TYPICAL APPLICATIO
CSS1 0.01F CITH1A 100P CITH1 1200pF 39pF
RITH1 10k RA1 68.1k
RB1 215k ITH1 VFB1
C1 1nF
C2 1nF RA2 40k CITH2 330P RITH2 15k RB2 125k
SENSE2 - SENSE2 + VFB2 ITH2 TRACK/SS2
INTVCC BG2 BOOST2 SW2 TG2 FOLDDIS D2 CB2 0.47F
CITH2A 100P CSS2 0.01F
MTOP1, MTOP2, MBOT1, MBOT2: Si7848DP L1: CDEP105-3R2M L2: CDEP105-7R2M COUT1, COUT2 = SANYO 10TPD150M
RELATED PARTS
PART NUMBER LTC1628/LTC1628-PG/ LTC1628-SYNC LTC1735 LTC1778/LTC1778-1 LT1976 LTC3708 LTC3727/LTC3727A-1 LTC3728 LTC3729 LTC3731 DESCRIPTION 2-Phase, Dual Output Synchronous Step-Down DC/DC Controller High Efficiency Synchronous Step-Down Switching Regulator No RSENSE Current Mode Synchronous Step-Down Controllers Dual, 2-Phase, DC/DC Controller with Output Tracking 2-Phase Dual Synchronous Controller Dual, 550kHz, 2-Phase Synchronous Step-Down Controller 20A to 200A, 550kHz PolyPhase(R) Synchronous Controller 3- to 12-Phase Step-Down Synchronous Controller COMMENTS Reduces CIN and COUT, Power Good Output Signal, Synchronizable, 3.5V VIN 36V, IOUT up to 20A, 0.8V VOUT 5V Output Fault Protection, 16-Pin SSOP Up to 97% Efficiency, 4V VIN 36V, 0.8V VOUT (0.9)(VIN), IOUT up to 20A Current Mode, No RSENSE, Up/Down Tracking, Synchronizable 0.8V VOUT 14V; 4V VIN 36V Dual 180 Phased Controllers, VIN 3.5V to 35V, 99% Duty Cycle, 5x5QFN, SSOP-28 Expandable from 2-Phase to 12-Phase, Uses all Surface Mount Components, VIN up to 36V 60A to 240A Output Current, 0.6V VOUT 6V, 4.5V VIN 32V
3827f
PolyPhase is a registered trademark of Linear Technology Corporation. No RSENSE is a trademark of Linear Technology Corporation.
32 Linear Technology Corporation
(408) 432-1900 FAX: (408) 434-0507
1630 McCarthy Blvd., Milpitas, CA 95035-7417
www.linear.com
+
U
High Efficiency Dual 3.3V/8V Step-Down Converter
LTC3827 TRACK/SS1 PGOOD2 PGOOD1 TG1 SW1 CB1 0.47F PLLLPF PHASMD CLKOUT PLLIN/MODE SGND RUN1 RUN2 EXTVCC CINT2 1F CINT1 4.7F VIN PGND CIN1 10F CIN2 10F BOOST1 BG1 D1 VIN 12V MBOT1 MTOP1 L1 1.5H RSNS1 5m COUT1 150F X2 VOUT1 3.3V 10A 100k 100k SENSE1 + SENSE1 - MTOP2 L2 7.2H RSNS2 15m COUT2 150F MBOT2 VOUT2 8V 2A
3827 TA06
LT 1205 * PRINTED IN USA
(c) LINEAR TECHNOLOGY CORPORATION 2005

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